Exemplary embodiments relate to an electronic circuit. In particular, exemplary embodiments relate to a system interconnect for connecting a plurality of master devices and a plurality of slave devices, and an operating method of the system interconnect.
Recently, a related art system-on-chip has been widely used. The related art system-on-chip includes a plurality of chips that are integrated on a chip and have different functions. In a design of the related art system-on-chip, it is essential to reduce a time necessary for development to cope with rapidly changing needs of the market. A technique of recycling a related art circuit block, that is, an intellectual property (IP) core may have been employed. The recycling of the IP core enables a time taken to develop products to be shortened and the reliability of the system-on-chip to be improved.
To design the system-on-chip effectively, the choice of interconnect for intercommunication among IP cores integrated on a chip is paramount. In the related art system-on-chip, the Advanced Microcontroller Bus Architecture (AMBA) bus of the Advanced RISC Machine (ARM) company is currently used as typical interconnect. The AMBA bus 2.0 includes Advanced High-Performance Bus (AHB) as a system bus and Advanced Peripheral Bus (APB) for connection with a peripheral device.
A pipelined operation, a multiple bus master, a burst transfer, and a split transaction characterize the AHB. However, when a master occupies a bus via the AHB, another master does not access a slave. That is, bus latency becomes longer in a system where a plurality of master devices is activated at the same time. The AXI protocol for making up for such a drawback and efficiently using a bus structure is defined in the AMBA 3.0 standard.
If an operating performance of the system bus is improved, operating performance of the overall system-on-chip is improved. Thus, there is a need for a system bus with improved operating performance.